1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for accelerating the writing of data from a slow bus to a fast bus.
2. History of the Prior Art
Historically, personal computers have utilized a single bus to transfer data between different internal components of the system. In personal computers using central processing units (CPUs) designed and manufactured by Intel Corporation of Santa Clara, Calif., such buses have typically been designed as either an Industry Standard Association (ISA) bus or an Expanded Industry Standard Association (EISA) bus. The ISA bus is a sixteen bit data bus while the EISA bus is thirty-two bits wide. Both the ISA bus and the EISA bus typically operate at a frequency just over eight megahertz. These bus widths and the rates at which each of these buses is capable of operating have limited the speed at which a computer can operate so there have been a number of attempts to increase bus speed.
One recently implemented method of increasing bus speed is to provide an additional, so called, "local bus" which is more closely associated with the central processor than either of the above-mentioned buses and which is capable of running at speeds closer to the speeds at which the processor itself runs. Those system components which require faster operation than has been available using the slower buses (such as an output display card driving an output display device) are joined to this faster local bus. The slower ISA or EISA bus is continued in essentially unchanged form as a secondary bus, and those components which are able to tolerate longer access times are associated with the slower bus. Although the theory behind using a local bus is good, many local bus designs have actually slowed the operation of the computer in some respects.
Intel Corporation has designed a new local bus which may be associated in a computer system both with an Intel processor and with other buses such as an ISA bus or an EISA bus (each of which is hereinafter referred to broadly as a secondary bus). This new local bus is able to transfer data more rapidly for selected components of the system without the conflicts and bottlenecks which arise using other local bus systems. This new bus is referred to as the "peripheral component interconnect" (PCI) bus. The PCI bus is thirty-two bits wide and is capable of operating at either twenty-five or thirty-three megahertz.
A computer system using the PCI bus includes, in addition to the physical PCI bus, a first circuit, referred to as a "bridge" circuit, which controls the transfer of data between the PCI bus, the central processing unit, and main memory. A second bridge circuit is also arranged to control the transfer of data between the secondary bus and the PCI bus. Thus, the arrangement is such that components on the PCI bus utilize the first bridge in transfers of data involving the central processor or main memory. On the other hand, components on the secondary bus utilize the second bridge circuit, the PCI bus, and the first bridge in transfers of data involving the central processor or main memory; and utilize the second bridge and the PCI bus in transfers of data involving the components on the PCI bus.
Modern computer systems have also attempted to utilize bus masters to speed the operation of the system. A bus master is a component capable of originating and controlling the transfer of data on a bus. Typically a bus master includes a bus controller and operates on its own internal clock. Bus masters may be associated with either the PCI bus or the secondary bus in a computer system using a PCI bus. A peculiarity of the ISA and the EISA buses is that once a bus master (such as a DMA unit) has gained control of the bus, it cannot be forced off the bus until it has completed its operation. When the secondary bus master has gained access to the secondary bus in an operation which involves the PCI bus, the secondary bus master cannot be forced off the PCI bus until it has completed its operation. In such a case, since the secondary bus master cannot be forced to relinquish control of either the secondary or the PCI bus until it has completed its operation, operations on the PCI bus must be stopped until the operation on the secondary bus has been completed. Since the rate of transfer on the ISA bus is either one-sixth or one-eighth the rate of transfer on the PCI bus depending on the PCI bus rate, it is very desirable that the bridge circuitry joining these two buses transfer data from the slower secondary bus to the faster PCI bus as swiftly as possible so that the PCI bus will not be slowed to the operational speed of the slower secondary bus.